Error detection and/or correction is a common feature in electronic systems, particularly in the memory controllers of computer systems. Therefore, methods and apparatus for validating the functionality of these features are needed. A well known way to validate error detection/correction functionality is to insert an error signal onto a signal line within the system, and then determine if the system responds properly to the error signal. A prior approach to inserting an error signal onto a bidirectional signal line involves determining the expected state and direction of the signals on the signal line at any given time by tracking the transactions occurring over the bidirectional signal line, then overdriving the master of the bidirectional signal line with the error signal at an appropriate time.
One problem with this approach is that the logic needed to track the transactions on the bidirectional signal line is typically quite complex. Another problem with this approach is that the error insertion is synchronized to specific activity on the bidirectional signal line, so errors can only be inserted at specific times, thus limiting the randomness of the validation effort. A third problem with this approach is that the need to overdrive masters of differing drive strengths leads to a design choice of either increasing the cost or decreasing the capability of the error insertion driver hardware.
Therefore, a novel approach to inserting an error signal onto a bidirectional signal line has been developed.